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KalEdge-Lite

Neural Network Compression & FPGA Deployment Framework

Model compression hls4ml FPGA deployment QAT · Pruning · KD HW-aware screening AI Agents Surrogate model

KalEdge-Lite is an end-to-end framework for neural network compression and FPGA deployment, accessible through a web-based interface. It orchestrates the full pipeline: from dataset preparation and architecture definition to compression, synthesis, and resource estimation.

Compression pipeline

Multiple training strategies can be combined within a unified execution pipeline: pruning, TF-MOT quantization, QKeras quantization, QAT, QAP, and knowledge distillation; either as separate experiments or as hybrid sequential workflows. All trained models are available for download.

Hardware-aware screening & deployment

Each generated model is scored across task-level metrics (accuracy, model size, parameter count) using a configurable policy (FPGA-oriented, embedded, TinyML, or accuracy-driven). The top-ranked configuration is exported to a synthesizable HLS project via hls4ml. A lightweight analytical surrogate model then estimates latency and FPGA resource utilization without requiring full synthesis, enabling fast design-space exploration. The generated accelerator IP is automatically integrated into a preconfigured Vivado platform template, completing the ML-to-FPGA workflow.

1. Dataset loading Upload / select data 1 2. Architecture Manual Layers / filters Architect + Advisor AI agent search 2 3. Parameters LR · epochs · batch Quantization bits Pruning ratio Distillation T Training config 3 4. Training pipeline Baseline — FP32 Full precision Separate techniques PTQ · QAT · Pruning · KD Unified QAT + Pruning + KD ⬇ Download all models .h5 / .pt / .onnx per technique 4 5. Report & model selection Accuracy · F1 Size · Latency Compression ratio Best model by score HLS conversion 5 6. hls4ml integration No interface Bare HLS core — no AXI DMA interface AXI-Stream / DMA transfer ComBlock interface Communication block HLS project + confusion matrix Vivado / Vitis ready 6 7. HW resource estimator LUT · FF · BRAM · DSP Latency cycles FPGA utilization report 7

End-to-end KalEdge-Lite application flow

Launch KalEdge-Lite [Coming soon]
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